Youssef Ramzy Senior Software Engineer

A

An 8x8 carry save multipiler

Dec 2015

it was one of our year work. we were asked to design an 8x8 carry save multipiler using matlab-simulink-verilog and we add some optimization and implement in on fpga.

i

image compression using DCT

Dec 2015

We use DCT high capablity to compress data for image comression

R

Run Time Verification

May 2015 - Oct 2016 (1 year 6 months)

it is based on synthesizable system Verilog assertions which are able to localize the bug and correct it online using mutation based repair. The code is on FPGA and if assertions discovered a bug, it will correct the LUT online and to need to recompile. This project is with co-operation with Mentor Graphics EGYPT.

B

Bell-triangle algorithm

May 2015

Building Bell-triangle algorithm using assembly language of 8086/8088 microprocessor

L

LTI system

May 2015

Building a LTI(Linear Time Invariant) system using MATLAB codes

I

Ink-jet printed RFID antenna

Jan 2015

Design and implementation of Ink-jet printed RFID antenna on paper substrate aimed to wearable application under supervision of VT-MENA (Virginia Tech) lab in Alex University

M

MIT Coffee Can Radar

Aug 2014

The project included making a continuous radar system with a transmitter and receiver made from coffee canes. After the received signal passes with both analog and digital circuits it passes to computer with a Matlab code to calculate the distance and the speed of the target body. The largest distance the radar can measure is about 70 meter after it the measurements the calculations will have a big errors.

G

GPU

Mar 2014

Building a GPU under supervision of Dr. Maged Ghonima. I am a one of the architecture team that has a task to build the architecture of the system. My role is understanding the Rasterization module in the system and trying to build its architecture

A

AES-CTR IP accelerator

Feb 2014

Developing two different IPs for AES-CTR to cover possible requirements for low area/low data rate and high data rate/low area. I have made the project in 10 days under supervision of Dr.Ahmed Shalaby and Dr.Mohamed Morsy in (E-JUST) with a team of 5 students.

S

SPqM

Feb 2014

An embedded system to monitor the client queue in front of the tellers. Under supervision of Dr. Ahmed Shalaby at E-just in 2nd year

C

Ciena Design Engine

Converted a monolithic Flask/Angular app into a high available/scalable solution. It automates the creation of detailed network design and the creation of configuration files to be used for commissioning new network equipment. Created a CI/CD pipeline and utilized AWS (ECR – ECS – RDS – S3) as a deployment infrastructure.

C

Coffee Can Radar (MIT Student Project)

** This project was taken from MIT institute aims to lean the basics of RADAR system with very low cost as possible. ** Our goal is to create a laptop based low-cost, low-power range-Doppler imaging system based on an existing coffee can cantenna design. The actual radar hardware is based on an existing design that is currently being used in a Massachusetts Institute of Technology Lincoln Laboratory Opencourseware course. ** The existing design sends analog radar data to a PC via the audio line-in port. The data is saved on the PC as a .wav le. The user can then process the data using a MATLAB script to display range and velocity measurements. A problem with this set-up is that the data cannot be processed in real time. The user must record

R

Run Time Verication methodology Based on system verilog assertions synthesis with mutation based auto-correction | Gradu

** Worked on the methodology synthesizing Systemverilog assertions to FPGA platform used for run time verication using Dynamic partial recongurations.. ** By inserting assertions in the verilog design want to be verified as golden model and convert the implemented assertions by our compiler to synthesized verilog design. ** Divide the asserted design on the FPFG to implement the assertions on the static part while the design on the dynamic part to be able to replace it if there is any error detected by the assertions using mutations. ** Using TCL and perl scribets to control the bit stream generated to FPGA with the corrected mutation. ## Responsible for Built up the SystemVerilog Assertions Synthesis Compiler using Perl scripts and develop

S

SystemVerilog Assertions Synthesis Compiler | Gradation project

** The Compiler used for translating system verilog les contains assertions to verilog files contains synthesized modules make the function of assertions. ** The proposed compiler uses several Perl scripts, to read the assertion sequences and property, then brings the appropriate module from a pre-designed list of Verilog modules for each operator according to the sequence/ property used operator, and finally interconnects modules in the right order,while developing the required Verilog/ Perl files. # Responsible for implementing Relational operators of concurrent assertions into verilog synthesized modules. # Responsible for Creating generic Perl scripts to pares the sequences lines into each verilog modules after modifying it according ea

A

AES-CTR hardware accelerator IP

As part of a Digital design program I was part of a team assigned to develop two different IPs for Advanced Encryption Standard Counter mode to cover possible requirements from low area/low data rate solution and high data rate/ large area solution. The verification process was decided to be done using ModelSim – Matlab link. This project was under supervision of Dr.Ahmed Shalaby & Dr.Mohamed Morsy as a Final project in the Digital Design training program held in E-JUST . I worked in a team of 5 students, and I designed the Key expansion block for the low power IP and the Top module.

F

Face recognition

Studying a face recognition system by using the concept of eigen faces using MATLAB code

A

AES Accelerator

Developing two different IPs for AES-CTR to cover possible requirements for low area/low data rate and high data rate/low area. I have made the project in 10 days under supervision of Dr.Ahmed Shalaby and Dr.Mohamed Morsy in (E-JUST) with a team of 5 students. My role was to design the Mixcolumn multiplier.

R

Run Time Verication methodology Based on system verilog assertions synthesis with mutation based auto-correction

Worked on the methodology synthesizing Systemverilog assertions to FPGA platform used for run time verication using Dynamic partial recongurations. Responsible for handling auto correction based on mutation using static slicing, backward tracing and ranking approaches using perl scripting as main platform.

Q

Quadcopter project

It was required to design a full Quad-Copter system without any implementation of Micro-Controllers. Just using Logic ICs and we got a grade of 110%

c

communication systems

simulating an analog communication systems using MATLAB.

Youssef Ramzy

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