Srinivasan Gomadam Ramesh

Software Engineer (Al/Data)

Quadrant Technologies

Jul 2025 - Current (1 year)

• Architected an end-to-end Al Resume Intelligence Platform on Azure, designing hybrid RAG pipelines with Qdrant Db vector embeddings and LLM orchestration to automate structured skill extraction from unstructured resumes achieving 95% content accuracy across PDF, DOCX, and image-based formats at production scale. • Engineered LLM inference pipelines using Cerebras-hosted GPT OSS 120B and open source VLM (Qwen and Gemini to analyze resume layouts and auto-generate editable templates via Jinja2 and structured JSON schemas eliminating manual formatting effort for downstream hiring workflows. • Delivered production-ready microservices and CI/CD infrastructure using FastAPI, Docker, and Azure DevOps implementing schema validation, automated tes

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Data Analyst/Engineer

Sports Excitement

Feb 2025 - Jul 2025 (6 months)

• Conducted competitive analysis across 10+ sports platforms to identify feature gaps and user experience shortfalls synthesizing findings into actionable product recommendations that directly influenced roadmap prioritization and go-to-market strategy for the platforms core engagement features. • Engineered automated web scraping pipelines using Python, Selenium, and Beautiful Soup to systematically collect structured sports program and contact data from university portals that streamlined outbound marketing outreach and reduced manual prospecting effort. • Designed and implemented a relational data model in PostgreSQL (Supabase) with normalized transactional tables and OLAP oriented fact tables for user session, engagement, and ad perform

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Research Assistant

Texas Analog Center

Sep 2023 - Dec 2024 (1 year 4 months)

• Conducted accelerated TDDB (Time-Dependent Dielectric Breakdown) reliability testing on high-voltage isolation ICs under a UTD Texas Instruments research collaboration applying continuous AC stress via AR7715 high pot tester and Trek 20/20 HV amplifier across IC devices at voltage levels, recording Time-to-Fail (TTF) datasets that fed Weibull β/η parameter extraction and E-field lifetime extrapolation models directly supporting IEC 60747 qualification for Tl isolation products targeting high-power GaN applications in Al data center infrastructure. • Engineered automated test instrumentation pipelines using Python, PyVISA, and GPIB interfaces to control ATE hardware, acquire multi-channel sensor data, and process structured TTF datasets wi

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Project Analyst

Indian Institute of Technology (IIT)

Jan 2022 - Nov 2022 (11 months)

• Diagnosed 3+ years of unresolved faults in ABB medium-voltage Banbury drive systems at a large manufacturing facility applied Python and MATLAB clustering models to operational field data to detect anomaly patterns and correlate failure signatures with Simulink simulations, isolating root causes within 6 months and delivering corrective actions that reduced unplanned downtime and generated $2M in annual savings. • Validated EV charger (EVSE) designs for a startup against IEC 61851 international compliance standards developed structured test protocols for power electronics subsystems, characterized IGBT gate drivers and SiC MOSFETs via double-pulse testing, and recommended targeted design improvements that reduced compliance failure rate b

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Senior Engineer

Rane Brake Lining Ltd-R&D

Jul 2018 - Sep 2021 (3 years 3 months)

• Designed interactive Power BI dashboards for monitoring the performance KPIs (MTTR, MTBF, MTTF), increasing equipment availability by 15% and accelerating data-driven decision-making. • Built a Power Apps incident reporting system integrated with SharePoint and Power Automate to digitize field safety workflows replacing manual processes with automated routing and real-time dashboards, improving shop- floor safety compliance. • Improved testing asset availability from 80% to 91% by diagnosing and resolving 360+ complex hardware- software equipment failures within SLA, including control system faults, sensor calibration issues, and interface communication errors, increasing annual productivity by 15%. • Engineered NI-cDAQ and LabVIEW data a

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Undergraduate Researcher / Project Internship

IIT Madras

Sep 2017 - May 2018 (9 months)

• Design and Testing of Parasitic Element Measurement Circuit: Worked at the Machine and Drives Laboratory under the guidance of Dr. Kamalesh Hatua on a project on power electronics applications. • Hardware Design and Pulse Generation: Developed a digital double pulse generation board using Intel Quartus and Intel MAX 10 FPGA evaluation boards to test gate driver characteristics.

Srinivasan Gomadam Ramesh

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