ASIC Design Verification Engineer at SHAKTECH CORP

About the RoleWe are seeking an ASIC Design Verification Engineer to verify the functionality, performance, and robustness of our custom silicon designs. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.ResponsibilitiesDevelop and execute verification plans for block, subsystem, and full-chip environments.Build SystemVerilog/UVM test benches (agents, monitors, scoreboards, checkers, coverage models).Write SystemVerilog Assertions (SVA) and integrate formal verification.Drive constrained-random and directed testing strategies.Run simulations, triage failures, and collaborate with RTL designers.Implement and maintain coverage models for sign-off.Manage regression testing, CI pipelines, and simulation farms.Participate in design reviews and microarchitecture discussions.QualificationsB.S./M.S. in Electrical Engineering, Computer Engineering, or related field.3+ years of ASIC/SoC verification experience.Strong knowledge of SystemVerilog, digital logic, and verification flows.Proficiency with simulation tools (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), and coverage tools.Experience with scripting (Python, Perl, TCL) and Git.

ASIC Design Verification Engineer

Emma

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www.shaktechcorp.com/

Admin access needed