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Responsibilities
We are seeking a highly experienced ASIC/NIC Validation Engineer to develop and execute tests for networking silicon supporting large-scale distributed AI workloads. The role focuses on RDMA, RoCE v2, NCCL collective communications, networking ASICs/NICs, and multi-node validation across emulation, FPGA, and silicon platforms.Key Responsibilities:Develop and maintain tests for AllReduce, AllGather, ReduceScatter, and AllToAll operations.Create RDMA Verbs-level tests covering positive, negative, and error scenarios.Validate multi-node and multi-NIC communication across different network topologies.Develop traffic-generation and data-validation tools for RDMA workloads.Automate testing using C/C++ and Python and integrate tests into CI/CD pipelines.Execute and analyze NCCL-tests, perftest, and RDMA benchmarks.Debug issues across ASIC RTL, firmware, drivers, rdma-core, and user-space communication libraries.Work with architecture, firmware, driver, modeling, and validation teams.Required Skills:10+ years icon validation, or networking.5+ years testing networking ASICs, NICs, SmartNICs, or DPUs.5+ years with collective communication/distributed systems.Expert C/C++ and strong Python.Strong knowledge of RDMA, RoCE v2, NCCL/MPI, Ethernet/L2, PCIe, and collective operations.Experience with ASIC/silicon validation and preferably emulation/FPGA environments.Knowledge of QPs, CQs, MRs, PDs, RDMA READ/WRITE/SEND/RECEIVE.Experience with libibverbs/rdma-core is highly desirable.Education:B.S./M.S. ctrical Engineering, Computer Engineering, or a related field.
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