Senior RTL Design Engineer (FPGA) at Rapinno Tech Solutions Pvt Ltd | Torre
Senior RTL Design Engineer (FPGA)
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Senior RTL Design Engineer (FPGA)

Rapinno Tech Solutions Pvt Ltd
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Full-time

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Remote (anywhere)
Posted 7 months ago

Responsibilities

Senior RTL Design Engineer (FPGA) responsibilities include designing efficient RTL implementations for FPGAs in collaboration with system architects; translating MATLAB/Simulink models to RTL; developing RTL architecture & microarchitecture from algorithm requirements; implementing RTL using VHDL/Verilog/SystemVerilog; designing blocks such as ORAN, IP compression, digital filters, FFT engines, time synchronization protocols, JESD 2.5; performing functional verification, linting & synthesis; FPGA implementation & performance validation; collaborating with verification and firmware teams for end-to-end integration; supporting board bring-up & validation.
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