Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert h-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.What You Will DoUnderstand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency rangeArchitect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and SpectreAddress challenges h as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimizationSupervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologiesBe responsible for PLL bring up ducting performance characterization using state-of-the-art lab equipmentConduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologiesWhat You Will BringMaster’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience production level tape-out experience.Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLsProficient ctromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modellingStrong communication and documentation skillsAnnual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
5 days ago