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WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.Together, we advance your career.As a member of the AECG Product Validation and Solutions Team, you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High-speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives.The RoleAt AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen6/Gen7, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products.The PersonYou have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges.Key ResponsibilitiesDevelop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications marketsParticipate hitecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPsDevelop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plansPre-Silicon and Post Silicon validation for new PCIe enabled blocksResponsible for IP design, Silicon bring up, Validation and IP releaseWork in collaboration with the Global teamsPreferred ExperienceStrong knowledge ferably with Verilog and SystemVerilogProficient in RTL simulation tools (VCS, Modelsim)Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocolExperience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/AnalyzerExperience in developing system or IP prototypes using FPGAsStrong knowledge of IP/SOC design methodologiesExperience with scripting languages including Tcl, Perl, Python, Unix shells and MakefilesKnowledge of C/C++ is an added advantageACADEMIC CREDENTIALS:Bachelor's or Masters degree in Computer Engineering/Electrical Engineering with 8+Yrs of exp
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