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Feres Khigazi
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Red Sea, Egypt
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Résumé
Jobs
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Senior C++ Software DeveloperOrion InnovationMay 2022 - Current (4 years 4 months)• Designed and implemented video playback pipelines on set-top box devices using FFmpeg and GStreamer. • Worked with OTT streaming formats (HTTP Live Streaming/HLS, DASH), handling segment parsing and playback. • Implemented buffering and adaptive bitrate (ABR) logic to improve playback stability under varying network conditions. • Integrated DRM systems (Widevine, PlayReady) for protected content playback and debugged player issues in production, including startup delays, buffering, and playback failures. • Investigated and fixed audio/video synchronization issues and integrated and adapted third-party C++ components in constrained embedded environments, including WebAssembly builds using WASI-SDK and Emscripten.- Embedded Software DeveloperWest EngineeringNov 2019 - Apr 2022 (2 years 6 months)• Designed and implemented SIL-3 compliant safety-critical control software for a 1200 MW turbine, achieving <5ms deterministic loop timing for PID control and signal filtering, ensuring 99.99% operational uptime. • Developed fault-tolerant Layer 2/3 deterministic Ethernet protocols, reducing network jitter by 40% and ensuring sub-millisecond data synchronization across distributed DCS controllers. • Developed high-reliability Embedded C++ firmware on STM32 (ARM Cortex-M4) using FreeRTOS and LWIP, implementing custom TCP/IP stacks for real-time industrial telemetry. • Built and brought up PLC peripheral modules, covering hardware design, board bring-up, and firmware development.
- NJunior Embedded DeveloperNew Telecom TechnologiesJan 2019 - Oct 2019 (10 months)• Designed SAR imaging signal processing chains in C/C++ using High Level Synthesis (HLS), targeting deployment on high-performance FPGA/SoC platforms. • Performed hardware-aware optimization of DSP functions (such as FFTs or filters) to minimize latency and area while maintaining signal integrity. • Bridged the software-hardware gap by providing C-level test vectors and design constraints to support the VHDL development and integration cycle.
Education
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- PBachelor of Engineering, Telecommunications and Electronics EngineerPeter the Great St.Petersburg Polytechnic University, RussiaSep 2016 - Jun 2020 (3 years 10 months)