Anush Aghasyan

Anush Aghasyan

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ASIC Physical Design Engineer, Staff
Saskatchewan, Canada

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Résumé


Jobs verified_user 0% verified
  • Synopsys Inc
    ASIC Physical Design Engineer, Staff
    Synopsys Inc
    Jan 2020 - Current (6 years 6 months)
    Physical Design from netlist handoff to GDS tape out, including floor planning, place and route, clock tree synthesis, timing closure, physical verification and EMIR of ASIC blocks. EDA tools: Prime Time, Design Compiler, Formality, ICV, Calibre, StarRC, Custom Designer, ICC2. Application Engineer, Staff (2024/07-2025/01) •Customer support for DDR IPs, by Synopsys Rotation program
  • Virage Logic
    CAD Support Engineer
    Virage Logic
    Jul 2009 - Dec 2009 (6 months)
    Developed decks of different technologies and covered tool issues.
  • Synopsys Inc
    Build/Verification QA Engineer, Staff
    Synopsys Inc
    Jan 2009 - Jan 2020 (11 years 1 month)
    Quality Assurance (QA) and Final Build of different type of PHYs (DDR, HBM, etc). DDR PHY build, release management, DDR QA process supervision. Collaboration with other team members to complete all tasks and clear all issues during QA and Build process. Use of different verification tools (Hyperlinx, Corekit) during Build process. Work with PEMs on the ongoing projects to clarify Build related issues and to clean up the databases. Create schedules for DDR PHY component QA and Build tasks, maintain them and attend to conference calls.
  • Virage Logic
    Mask Design Engineer
    Virage Logic
    Jul 2007 - Jun 2009 (2 years)
    Analog and digital layout of DDR Memories and IOs.
Education verified_user 0% verified
  • S
    Master's degree, Microelectronic Circuits and Systems
    State Engineering University of Armenia Synopsys
    Jan 2006 - Jan 2008 (2 years 1 month)
  • S
    Bachelor's degree, Microelectronic Circuits and Systems
    State Engineering University of Armenia
    Jan 2002 - Jan 2006 (4 years 1 month)